← clockd → cpins

CADR – PC, SPC CONTROL [contrl]

3E1874S323E2374S003D2874S003D2874S003D2874S003D2174S083D2874S003E2274S043D2174S083D26QUAD FF74S175QQQQQQQQCLK↑DDDDCLR4E3074S374E3074S373E0774S003D2174S084E3074S373E1474S083E27∧∧∧∧∨74S64AOI3F30∧∧∧∧∨74S64AOI0 SPC1 IR2 DPC3 IPC3E25∧∧∧∧∨74S64AOI3E2374S003E28∧∧∧∧∨74S64AOI3E26∧∧∧∧∨74S64AOI4D0974S083E2374S003E0974S323F20HEX INV74S043E2374S003E2474S083E2274S043E2474S083E2474S083E2474S083E2974S113E2974S11Dispatch R-bit is set. Ignore new PC, pop PC off the SPC stack.DRDispatch Enabled. Instruction is DISPATCH but not dispatch write.DISPENBJump Condition. Selected based on IR0-IR2, IR5 must be high.JCONDInstruction Register bit 6: JUMP: Invert ConditionIR6Jump Return. Set in a jump instruction with P set and R cleared.JRETJump Condition. Selected based on IR0-IR2, IR5 must be high.JCONDJump Return if False. Instruction is JUMP with R-bit set and condition inverted.JRETFIgnore POPJ. Instruction is a DISPATCH instruction and R-bit is cleared.IGNPOPJJump Condition. Selected based on IR0-IR2, IR5 must be high.JCONDInstruction Register bit 8: JUMP: P-bit, CallIR8Instruction Register bit 6: JUMP: Invert ConditionIR6Instruction Register contains a JUMP instruction (IR44-IR43).IRJUMPDispatch R-bit is set. Ignore new PC, pop PC off the SPC stack.DRDispatch P-bit is set. Save return address to SPC, jump to new PC address.DPDispatch Enabled. Instruction is DISPATCH but not dispatch write.DISPENBJump Condition. Selected based on IR0-IR2, IR5 must be high.JCONDJump Call if False. Instruction is JUMP with P-bit set and condition inverted.JCALFHI4DESTSPCStack PCSPCNTSPOPStack (PC) Push. High if destination is SPC, if jump call if false and condition is false, if dispatch enabled and P but not R, or if jump and not invert condition and P and condition is true.SPUSHStack (PC) Push. High if destination is SPC, if jump call if false and condition is false, if dispatch enabled and P but not R, or if jump and not invert condition and P and condition is true.SPUSHStack PCSPCENBSPOPInstruction Register bit 7: JUMP: N-Bit, NOPIR7Jump Condition. Selected based on IR0-IR2, IR5 must be high.JCONDInstruction Register bit 6: JUMP: Invert ConditionIR6Instruction Register contains a JUMP instruction (IR44-IR43).IRJUMPInstruction Register bit 7: JUMP: N-Bit, NOPIR7Jump Condition. Selected based on IR0-IR2, IR5 must be high.JCONDJump if False. Instruction is JUMP and condition is inverted.JFALSEDispatch N-bit is set. Inhibit execution of next instruction.DNDispatch Enabled. Instruction is DISPATCH but not dispatch write.DISPENBHI4Instruction Write Delayed. Set in the clock cycle after a jump instruction with P and R set.IWRITEDNext instruction will be NOPed.NSet on Parity Error if Traps are enabled via Spy or on Boot Trap.TRAPPC Source bit 0. False if popj, or dispatch and not fallthrough, or jump return if false and jump-condition is false, or jump return and jump condition and not jump invert condition. Used together with PCS1 to select the NPC bus source, 0=SPC, 1=IR, 2=DPC, 3=IPC.PCS0HI4Jump Condition. Selected based on IR0-IR2, IR5 must be high.JCONDInstruction Register bit 6: JUMP: Invert ConditionIR6Jump Return. Set in a jump instruction with P set and R cleared.JRETHI4Jump Condition. Selected based on IR0-IR2, IR5 must be high.JCONDJump Return if False. Instruction is JUMP with R-bit set and condition inverted.JRETFBoth P and R bit in dispatch instruction are set, fallthrough (do not dispatch)DFALLDispatch Enabled. Instruction is DISPATCH but not dispatch write.DISPENBHI4POPJ. High if the POPJ bit in the current instruction is high and the current instruction is not NOPed or if a delayed instruction write (IWRITED) is active.POPJPC Source bit 1. False if popj and not ignore popj, or jump if false and not jump condition, or instruction is jump and not invert condition and jump condition, or dispatch enabled and R-bit but not P-bit. Used together with PCS0 to select the NPC bus source, 0=SPC, 1=IR, 2=DPC, 3=IPC.PCS1HI4Dispatch P-bit is set. Save return address to SPC, jump to new PC address.DPDispatch R-bit is set. Ignore new PC, pop PC off the SPC stack.DRDispatch Enabled. Instruction is DISPATCH but not dispatch write.DISPENBJump Condition. Selected based on IR0-IR2, IR5 must be high.JCONDInstruction Register bit 6: JUMP: Invert ConditionIR6Instruction Register contains a JUMP instruction (IR44-IR43).IRJUMPJump Condition. Selected based on IR0-IR2, IR5 must be high.JCONDJump if False. Instruction is JUMP and condition is inverted.JFALSEIgnore POPJ. Instruction is a DISPATCH instruction and R-bit is cleared.IGNPOPJPOPJ. High if the POPJ bit in the current instruction is high and the current instruction is not NOPed or if a delayed instruction write (IWRITED) is active.POPJNOP A. Previous instruction or Spy interface NOPed the current instruction.NOPANOP11Instruction NOP. Previous instruction NOPed the current instruction.INOPPrevious instruction, Spy interface or a Trap NOPed the current instruction.NOPSet on Parity Error if Traps are enabled via Spy or on Boot Trap.TRAPNOP A. Previous instruction or Spy interface NOPed the current instruction.NOPADestination SPC delayed. Set in the clock cycle after DESTSPC was set.DESTSPCDDestination SPC delayed. Set in the clock cycle after DESTSPC was set.DESTSPCDStack PCSPCDRIVEStack PCSPCENBStack PCSPCENBTristate Enable. Alias of TPTSE.TSE3ASRCSPCPOPSRCSPCStack PCSPCDRIVETristate Enable. Alias of TPTSE.TSE3AStack PCSPCPASSTristate Enable. Alias of TPTSE.TSE3ASPUSHDTristate Enable. Alias of TPTSE.TSE3ASPUSHDSPC Write. The PC value that is written to the SPC stack.SPCWPASSSPC Write. The PC value that is written to the SPC stack.SPCWPASSTristate Enable. Alias of TPTSE.TSE3ASPUSHDPrevious instruction, Spy interface or a Trap NOPed the current instruction.NOPInstruction Register bit 42: POPJ-bit, Return after next instruction.IR42Previous instruction, Spy interface or a Trap NOPed the current instruction.NOPPrevious instruction, Spy interface or a Trap NOPed the current instruction.NOPSWPBSWPAWP4CSPUSHDWP4CSPUSHDNCNext instruction will be NOPed.NInstruction NOP. Previous instruction NOPed the current instruction.INOPInstruction NOP. Previous instruction NOPed the current instruction.INOPNCNCInstruction Write Delayed. Set in the clock cycle after a jump instruction with P and R set.IWRITEDPOPJ. High if the POPJ bit in the current instruction is high and the current instruction is not NOPed or if a delayed instruction write (IWRITED) is active.POPJInstruction POPJ. POPJ bit is set and current instruction is not NOPed.IPOPJCLK3CRESETStack (PC) Push. High if destination is SPC, if jump call if false and condition is false, if dispatch enabled and P but not R, or if jump and not invert condition and P and condition is true.SPUSHSPUSHDSPUSHDInstruction Write Delayed. Set in the clock cycle after a jump instruction with P and R set.IWRITEDInstruction Write Delayed. Set in the clock cycle after a jump instruction with P and R set.IWRITEDInstruction Write. Set in a jump instruction with P and R set.IWRITEIgnore POPJ. Instruction is a DISPATCH instruction and R-bit is cleared.IGNPOPJDispatch R-bit is set. Ignore new PC, pop PC off the SPC stack.DRInstruction Register contains a DISPATCH instruction (IR44-IR43).IRDISPInstruction Write. Set in a jump instruction with P and R set.IWRITEInstruction Register bit 9: JUMP: R-bit, ReturnIR9Instruction Register bit 8: JUMP: P-bit, CallIR8Instruction Register contains a JUMP instruction (IR44-IR43).IRJUMPJump Return. Set in a jump instruction with P set and R cleared.JRETInstruction Register bit 9: JUMP: R-bit, ReturnIR9Instruction Register bit 8: JUMP: P-bit, CallIR8Instruction Register contains a JUMP instruction (IR44-IR43).IRJUMPJump Return if False. Instruction is JUMP with R-bit set and condition inverted.JRETFInstruction Register bit 6: JUMP: Invert ConditionIR6Jump Return. Set in a jump instruction with P set and R cleared.JRETJump Call if False. Instruction is JUMP with P-bit set and condition inverted.JCALFInstruction Register bit 8: JUMP: P-bit, CallIR8Jump if False. Instruction is JUMP and condition is inverted.JFALSEJump if False. Instruction is JUMP and condition is inverted.JFALSEInstruction Register bit 6: JUMP: Invert ConditionIR6Instruction Register contains a JUMP instruction (IR44-IR43).IRJUMPDESTSPCDESTSPCDispatch Enabled. Instruction is DISPATCH but not dispatch write.DISPENBMiscellaneous Function bit 2. Decoded from IR10-IR11. DISPATCH: Write dispatch memory.FUNCT2Instruction Register contains a DISPATCH instruction (IR44-IR43).IRDISPBoth P and R bit in dispatch instruction are set, fallthrough (do not dispatch)DFALLDispatch P-bit is set. Save return address to SPC, jump to new PC address.DPDispatch R-bit is set. Ignore new PC, pop PC off the SPC stack.DRDispatch R-bit is set. Ignore new PC, pop PC off the SPC stack.DRDispatch P-bit is set. Save return address to SPC, jump to new PC address.DPStack (PC) Push. High if destination is SPC, if jump call if false and condition is false, if dispatch enabled and P but not R, or if jump and not invert condition and P and condition is true.SPUSHInstruction Register bit 6: JUMP: Invert ConditionIR6Instruction Register bit 8: JUMP: P-bit, CallIR8POPJ. High if the POPJ bit in the current instruction is high and the current instruction is not NOPed or if a delayed instruction write (IWRITED) is active.POPJPOPJ. High if the POPJ bit in the current instruction is high and the current instruction is not NOPed or if a delayed instruction write (IWRITED) is active.POPJInstruction Register bit 8: JUMP: P-bit, CallIR8Instruction Register bit 6: JUMP: Invert ConditionIR6Stack (PC) Push. High if destination is SPC, if jump call if false and condition is false, if dispatch enabled and P but not R, or if jump and not invert condition and P and condition is true.SPUSHDispatch P-bit is set. Save return address to SPC, jump to new PC address.DPDispatch R-bit is set. Ignore new PC, pop PC off the SPC stack.DRPrevious instruction, Spy interface or a Trap NOPed the current instruction.NOPSRCSPCPOPSRCSPCPOPREALPOPJ. High if the POPJ bit in the current instruction is high and the current instruction is not NOPed or if a delayed instruction write (IWRITED) is active.POPJHI4Dispatch P-bit is set. Save return address to SPC, jump to new PC address.DP2≡1≡3≡11≡13≡12≡3≡1≡2≡5≡4≡6≡9≡10≡8≡2≡1≡3≡12≡13≡11≡4≡3≡5≡4≡6≡4:5:12:13:1:9:14:15:10:11:7:6:2:3:6≡5≡4≡8≡9≡10≡5≡4≡6≡9≡10≡8≡3≡2≡1≡12≡13≡11≡1≡11≡12≡13≡4≡5≡6≡2≡3≡9≡10≡8≡1≡11≡12≡13≡4≡5≡6≡2≡3≡9≡10≡8≡1≡11≡12≡13≡4≡5≡6≡2≡3≡9≡10≡8≡6≡4≡5≡1≡11≡12≡13≡4≡5≡6≡2≡3≡9≡10≡8≡1≡11≡12≡13≡4≡5≡6≡2≡3≡9≡10≡8≡2≡1≡3≡8≡10≡9≡2≡1≡3≡1≡3≡5≡9≡11≡13≡2≡4≡6≡8≡10≡12≡2≡1≡3≡2≡1≡3≡2≡1≡5≡4≡6≡9≡10≡8≡12≡13≡11≡1≡2≡13≡12≡4≡3≡5≡6≡

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