← ior → iram00

CADR – IR PARITY [ipar]

3F2212 INPARITY93S48PEPO3E0212 INPARITY93S48PEPO3E2112 INPARITY93S48PEPO3F2412 INPARITY93S48PEPO3E0412 INPARITY93S48PEPO4E0374S32IPAROKIMODDIPARITYIPARITYGNDGNDGNDGNDGNDGNDGNDIR48IPAR3IPAR2IPAR1IPAR0NCNCIPAR0IPAR1NCNCIPAR2IPAR3NCIR47IR46IR45IR44IR43Instruction Register bit 42: POPJ-bit, Return after next instruction.IR42IR41IR40IR39IR38IR37IR36IR35IR34IR33IR32IR31IR30IR29IR28IR27IR26Instruction Register bit 25: DISPATCH: L-PC flag. Alter return address pushed on SPC by the CALL transfer type, if the N bit is set, to be the address of this instruction rather than the next instruction.IR25IR24IR23IR22IR21IR20IR19IR18IR17IR16IR15IR14Output Bus Control. With IR12. 1 ALU; 2 ALU shifted right by one bit, with the correct sign shifted in; 3 ALU shifted left by one bit, shifting in Q31 from the right.IR13Output Bus Control. With IR13. 1 ALU; 2 ALU shifted right by one bit, with the correct sign shifted in; 3 ALU shifted left by one bit, shifting in Q31 from the right.IR12IR11IR10Instruction Register bit 9: JUMP: R-bit, ReturnIR9Instruction Register bit 8: JUMP: P-bit, CallIR8Instruction Register bit 7: JUMP: N-Bit, NOPIR7Instruction Register bit 6: JUMP: Invert ConditionIR6Instruction Register bit 5: JUMP: If low, rotation count for M source. If high, condition number.IR5IR4IR3Instruction Register bit 2: ALU: Carry this bit into the low end of the ALU.IR2Instruction Register bit 1: ALU: Q control. 0 Do nothing; 1 Shift Q left, shifting in the inverse of the sign of the ALU output (ALU31); 2 shift Q right, shifting in the low bit of the ALU output (ALU0); 3 Load Q from ALU outputIR1IR011:12:13:14:15:1:2:3:4:5:6:7:10:9:11:12:13:14:15:1:2:3:4:5:6:7:10:9:11:12:13:14:15:1:2:3:4:5:6:7:10:9:11:12:13:14:15:1:2:3:4:5:6:7:10:9:11:12:13:14:15:1:2:3:4:5:6:7:10:9:5≡6≡4≡

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